The present invention relates to a SAW (Surface Acoustic Wave) convolver having a multi-layer structure consisting of a piezoelectric layer, insulator layer and a semi-conductor layer constituted to be arranged along a vertical direction, more particularly to such convolver in which an electrical bias voltage for the desired convolution efficiency therefore, can be easily obtained.
Conventionally, there has been known a bias circuit for applying bias voltage to a convolver, such as shown in FIGS. 1 and 2. For example, principle of the circuit shown in FIG. 1 has been already disclosed in Japanese Patent Provisional Publication SHO 63-52509 and SHO 6377177, while, principle of the circuit in FIG. 2 has been already disclosed in Japanese Patent Provisional Publication HEI 2-69013.
FIGS. 3 through 5 show structure of a convolver 1 to which bias voltage is to be applied from these bias circuits, principle of such a convolver has been already disclosed in Japanese Patent Provisional Publication SHO 63-62281. FIG. 3 shows a perspective view of the convolver 1 and FIGS. 4 and 5 respectively show sectional views of the convolver 1. In FIG. 4, a semi-conductor layer 19 comprises two layers arranged to be overlapped with each other, that is, a low-concentration semi-conductor epitaxial layer 21 and a high-concentration semi-conductor substrate 22. On the other hand, in FIG. 5, a bulk substrate is used as the semi-conductor layer 19. Both of these two constitutions of the semi-conductor layer 19 can be employed in the convolver 1. In practical use, the constitution shown in FIG. 5 is mainly employed since higher convolution efficiency can be obtained by means of the constitution of FIG. 5 as compared with the case in which the constitution shown in FIG. 4 is employed.
In the drawings of FIGS. 3 through 5, numeral 2 indicates a gate electrode formed on a piezoelectric film 17, two pairs of numerals 3, 3 indicate input terminals through which input signal is applied to the convolver 1 and numeral 4 indicates an output terminal through which output signal is taken out therefrom. Further, a pair of numerals 16, 16 indicate comb-shaped electrodes formed on the piezoelectric film 17, numeral 18 indicates an insulator layer for electrically insulating the piezoelectric layer 17 and the semi-conductor layer 19, and numeral 20 indicates a reverse side electrode provided at the opposite surface of the semi-conductor layer 19 to the surface on which the piezoelectric layer 18 is provided.
An operation of the conventional bias circuit will be described hereinafter with reference to the drawings of FIGS. 1 through 5.
In the circuit diagrams shown in FIGS. 1 and 2, characters "A" and "B" respectively indicate bias circuits arranged to be connected to the convolver 1 through a pair of connection terminals "a" and "b". Numeral 5 indicates an output matching circuit for taking impedance matching between the convolver 1 and a not-shown circuit to be connected thereto through the output terminal 4, numeral 6 indicates an oscillator for generating an AC (Alternating Current) signal at the desired frequency "f", numeral 7 indicates an amplifier for amplifying signal from a impedance bridge circuit, described later, numeral 8 indicates a differential amplifier arranged to output signal corresponding to difference of each input signals inputted to a pair of terminals 8-1 and 8-2 of the differential amplifier 8.
In the circuit "A" shown in FIG. 1, numeral 9 indicates a phase detector for detecting phase of the output signal from the amplifier 7 by comparing the phase of the signal with phase of the signal from the differential amplifier 8. The output signal from the differential amplifier 8 is fed to the phase detector 9 as a reference signal, as shown in FIG. 1. The phase detector 9 is further arranged to output signal corresponding to the phase of the signal from the amplifier 7. Numeral 10 indicates a DC (Direct Current) amplifier for amplifying signal from the phase detector 9 and numeral 11 indicates integrating circuit for integrating output signal from the DC amplifier 10.
In the circuit "B" shown in FIG. 2, numerals 12, 12 respectively indicate a wave-form shaping circuit for shaping wave form of signal from the amplifiers 7, 7, numeral 13 indicates phase comparator for comparing the phases of the signals from the wave-form shaping circuits 12, 12 and generating signal corresponding to the difference of the compared phases.
Numeral 14 indicates a charge pump circuit and numeral 15 indicates a low pass filter circuit respectively for generating signal corresponding to the output signal from the comparator 13.
In the circuits shown in FIGS. 1 and 2, an impedance bridge comprises a plurality of impedance units. Characters "Za, Zb, Zc, Zd and Zl" indicate fixed impedances having predetermined values, character "Zr" indicates a reference impedance. Character "Cc" in FIG. 2 indicates a capacitor for DC cut-off, and character "L" indicates a coil having a predetermined inductance.
Both of bias circuits "A" and "B" shown in FIGS. 1 and 2 are employable for applying bias voltage to the convolver 1. In this type of convolver 1, convolution efficiency "Ft" is changed in accordance with value of gate capacitance "C" generated between the gate 2 and the ground. The bias circuit, such as "A" or "B", is arranged to change the gate capacitance "C", therefore, the gate capacitance "C" is controlled so as to be fixed at desired value, for example "Cop".
In the bias circuits "A" and "B", value of "Zr" is arranged to be slightly variable. When the gate value "C" is to be changed, "Zr" is fixed at a certain value and the frequency "f" of the oscillator 6 is changed. As a result, the gate capacitance value "C" is determined at the desired "Cop", and then, convolution efficiency "Ft" corresponding to the "Cop" is obtained. In other words, by changing the value of the gate capacitance "C", the convolution efficiency "Ft" is changed.
FIG. 6 shows one example of a characteristic diagram, in a so-called ZnO/SiO2/n-Si structure type convolver, showing relations between the bias voltage "V" and the gate capacitance "C" as well as the convolution efficiency "Ft". The horizontal axis indicates variation of the bias voltage "V" and the vertical axis indicates variations of the gate capacitance "C" and the convolution efficiency "Ft". The gate capacitance "C" is indicated in relative representation. That is, the numeral "1" in a "C"-axis indicates capacitance under the condition that the bias voltage "V" is made sufficiently large. The capacitance "C" changes between "Cmax." and "Cmin.", as the gate voltage changes between an inversion region and a storage region through a sub threshold region and a depletion region. The C-V characteristic curve and Ft-V characteristic curve are indicated in this diagram. As the bias voltage "V" changes, i.e., the condition of the convolver is shifted between the inversion region and the storage region, the gate capacitance "C" and the convolution efficiency "Ft" are changed as shown in the diagram. As clearly shown in the diagram of FIG. 6, it is possible to set the gate capacitor "C" at "Cop" by setting the bias voltage "V" at "Vo", thereby setting the convolution efficiency "Ft" at the maximum value "Ftmax".
In this type of convolver, i.e., a piezoelectric film(Zno)insulator(SiO2)/semi-conductor(n-Si) structure type SAW convolver, electric charges can be injected into or released from the piezoelectric film layer. As a result, the C-V characteristic curve in the diagram of FIG. 6 shifts along the horizontal axis, i.e., the bias voltage axis, in accordance with an amount of the electric charge stored in the piezoelectric film layer. The Ft-V characteristic curve also shifts along the horizontal axis in a manner similar to the shift of the C-V characteristic curve. In other words, these characteristic curves simultaneously shift along the horizontal axis (the bias voltage axis) in accordance with the amount of electric charge stored in the piezoelectric film layer. Therefore, the value "Cop" corresponding to the "Ftmax" is fixed at constant value regardless of the variation of the amount of the electric charge.
As described above, by employing the bias circuit such as "A" and "B" shown in FIGS. 1 and 2, it is possible to maintain the convolution efficiency of the convolver at the maximum value "Ftmax" regardless of the amount of stored electric charge.
The above types of bias circuits exhibit the disadvantages described below.
First, in these types of bias circuit, it is necessary to detect the existing value of the gate capacitance "C" and then to set it at the desired value such as "Cop". As a consequence several types of electrical units such as oscillator, impedance bridge, phase detector, phase comparator are required. In order to detect the value of the gate capacitance "C", it is necessary to provide an oscillator 6 for generating an AC voltage to be applied to the gate electrode, and an impedance bridge. In order to set the gate capacitance "C" at the desired value, a phase detector 9, shown in FIG. 1, or a phase comparator, shown in FIG. 2, is required. Therefore, these circuits are complicated to use and they consume a large amount of electric power.
Secondly in these types of bias circuits, since an oscillator injects an AC signal, the output signal from the convolver is modulated by the AC signal. If amplitude of the AC signal is reduced, the amount of AC modulation in the output is also reduced. However, in this case, the overall feed back gain of the bias circuit must be increased for an appropriate detection of the gate capacitor "C". As a result of the high feed back gain, the bias circuit is liable to generate undesirable electrical oscillations.
Finally, these types of bias circuits include components which are not suitable for fabrication as part of a solid state integrated circuit. For example, the coil "L" in the bias circuit "B" shown in FIG. 2 is not conveniently included in an integrated circuit. As described previously, these circuits become complicated and their power consumption is high. Therefore, these circuits are not suitable for solid state implementation and miniaturization.